1. Field of the Invention
This invention generally relates to layout of integrated circuits (ICs), particularly resistor configuration.
2. Description of the Related Art
An electronic circuit is chemically and physically integrated into a substrate such as a silicon wafer by patterning regions in the substrate, and by patterning layers on the substrate. These regions and layers can be conductive, for conductor and resistor fabrication. They can also be of differing conductivity types, which is essential for transistor and diode fabrication. Degrees of resistance, capacitance, or conductivity are controllable, as are the physical dimensions and locations of the patterned regions and layers, making circuit integration possible.
In this disclosure, "n" denotes silicon that has been doped with atoms having more than four valence electrons (group V or higher), such as arsenic, which introduce negatively charged majority carriers into the silicon, and "p" denotes silicon doped with atoms having less than four valence electrons (group III or lower), such as boron or phosphorus, which introduce positively charged majority carriers. The majority charge carrier type is also referred to as conductivity type. A plus or minus superscript on an n or p indicates heavy or light doping, respectively. "Poly" denotes polycrystalline silicon, which is often used for resistor fabrication. Geometries and doping directly affect poly resistivity.
As illustrated in FIG. a typical IC input includes resistor R, which is usually configured as a poly layer adjacent to wirebond pad P as shown in FIG. 2. R and P are connected through contacts C. Typically, pad P rests on a layer of poly L which prevents short circuiting to substrate if pad P is punctured during wafer sort or assembly. R is also connected to other circuitry O in the IC. O generally will include input protection circuitry.